The use of stacked circuits comprising a plurality of series connected metal-oxide-semiconductor field-effect-transistors (MOSFETs) for logic functions is well known. FIG. 1 is a schematic diagram of a traditional stacked circuit 101 that performs an AND function.
The traditional stacked circuit 101 comprises in pertinent part an n-channel MOSFET (NFET) stack 103 coupled to a dynamic node pre-charge circuit 105 via a dynamic node 107. The NFET stack 103 comprises a first NFET 109 having a drain coupled to the dynamic node 107, a source coupled to a first node 111 and a gate which serves as an "A" input, a second NFET 113 having a drain coupled to the first node 111, a source coupled to a second node 115 and a gate which serves as a "B" input, and a third NFET 117 having a drain coupled to the second node 115, a source coupled to ground and a gate which serves as a clock (CLK) input.
The dynamic node pre-charge circuit 105 comprises a first p-channel MOSFET (PFET) 119 having a source coupled to a positive voltage rail (V.sub.DD), a drain coupled to the dynamic node 107 and a gate which serves as a CLK input; and a second PFET 121 having a source coupled to V.sub.DD, a drain coupled to the dynamic node 107 and a gate coupled to the dynamic node 107 via an inverter 123. An output of the inverter 123 serves as the output of the traditional stacked circuit 101.
Assuming the dynamic node 107 initially is uncharged, when a low voltage ("low") clock polarity is fed to each CLK input, the third NFET 117 is turned OFF and the first PFET 119 is turned ON. With the first PFET 119 ON, the dynamic node 107 charges toward the voltage V.sub.DD. As the dynamic node 107 charges toward V.sub.DD, the switching threshold of the inverter 123 is passed, the gate of the second PFET 121 is driven low and the second PFET 121 is turned ON to assist in the charging of the dynamic node 107.
With the dynamic node 107 charged to V.sub.DD, the output of the traditional stacked circuit 101 is driven to a low logic state via the inverter 123. Thereafter, when the CLK polarity is switched to a high voltage ("high") clock polarity, the third NFET 117 is turned ON (grounding the second node 115), the first PFET 119 is turned OFF, and the traditional stacked circuit 101's output logic state is dictated by the voltage states present on the A and the B inputs of the first NFET 109 and the second NFET 113, respectively. For instance, if the B input is held low, the second NFET 113 is OFF and no path can be created between the dynamic node 107 and ground whether the first NFET 109 is ON or OFF (e.g., whether the A input is held high or low). Therefore, the dynamic node 107 remains charged at V.sub.DD, and the output of the traditional stacked circuit 101 remains low. Similarly, if the A input is held low, the first NFET 109 is OFF and no path can be created between the dynamic node 107 and ground whether the second NFET 113 is ON or OFF (e.g., whether the B input is held high or low). The dynamic node 107, therefore, remains charged at V.sub.DD, and the output of the traditional stacked circuit 101 remains low.
Only when both the A input and the B input are driven high are both the first NFET 109 and the second NFET 113 turned ON, is a path created between the dynamic node 107 and ground, is the dynamic node 107 pulled low, and is the output of the traditional stacked circuit 101 switched from a low to a high logic state. The traditional stacked circuit 101 thus functions as an AND gate when the CLK input is held high as summarized in TABLE 1.
TABLE 1 A B OUT 0 0 0 0 1 0 1 0 0 1 1 1
The above described operation of the traditional stacked circuit 101 represents the "ideal" operation of the traditional stacked circuit 101. However, two phenomena known as "charge sharing" and the "bipolar effect" can cause the traditional stacked circuit 101 to deviate from its ideal behavior. Charge sharing is the unintentional transfer of charge from the dynamic node 107 that can cause the dynamic node 107 to be pulled below the switching threshold of the inverter 123 so that the traditional stacked circuit 101's output is erroneously switched to a high logic state. For instance, assume the CLK polarity is low, the first node 111 and the second node 115 are at a low voltage and the dynamic node 107 is charged to V.sub.DD. Ideally, if the CLK polarity is switched high, the A input is switched high and the B input is held low, the output of the traditional stacked circuit 101 remains low as shown in TABLE 1. However, with the first node 111 at a low voltage, when the first NFET 109 turns on due to the A input being held high, charge is transferred from the dynamic node 107 to the first node 111 (e.g., charge sharing occurs). The amount of charge transferred from the dynamic node 107 to the first node 111 depends on the ratio of the capacitances of the dynamic node 107 and the first node 111, but may be sufficient to pull the voltage of the dynamic node 107 below the switching threshold of the inverter 123 so that an erroneous high logic state is output by the traditional stacked circuit 101.
FIG. 2 is a schematic diagram of a conventional pre-charged stacked circuit 201 that overcomes the charge sharing problems of the traditional stacked circuit 101 of FIG. 1. The conventional pre-charged stacked circuit 201 comprises all of the components of the traditional stacked circuit 101, plus a third PFET 203 and a fourth PFET 205. The third PFET 203 has a source coupled to V.sub.DD, a drain coupled to the first node 111 and a gate which serves as a CLK input. The fourth PFET 205 has a source coupled to V.sub.DD, a drain coupled to the second node 115 and a gate which serves as a CLK input.
The conventional pre-charged stacked circuit 201 operates identically to the traditional stacked circuit 101 except that when the CLK polarity is low, both the third PFET 203 and the fourth PFET 205 are ON. Thus, the first node 111 and the second node 115 are "pre-charged" to V.sub.DD when the CLK polarity is low. Thereafter, when the CLK polarity is switched high, and if the A input is switched high and the B input is held low (the condition that resulted in charge sharing within the traditional stacked circuit 101), no charge sharing occurs between the dynamic node 107 and the first node 111 because the first node 111 is pre-charged to V.sub.DD. The dynamic node 107, therefore, remains charged at V.sub.DD, and the output of the conventional pre-charged stacked circuit 201 remains at its proper logic state (e.g., the low logic state as shown in TABLE 1). Both the traditional stacked circuit 101 and the conventional pre-charged stacked circuit 201, however, are susceptible to the bipolar effect if partially depleted silicon-on-insulator (SOI) transistors are employed for the NFETs 109-117 as described below.
The bipolar effect occurs when the parasitic bipolar transistor within an SOI MOSFET is inadvertently turned ON during an OFF state of the SOI MOSFET. As described below with reference to FIGS. 1-3, the bipolar effect can lead to erroneous switching of a conventional stacked circuit's output logic state.
FIG. 3 is a cross-sectional view of a typical SOI NFET 301 comprising a p-type bulk silicon region 303 having an oxide buried therein (e.g., a buried oxide 305) so as to form a top bulk silicon region 303a and a bottom bulk silicon region 303b. The top bulk silicon region 303a is surrounded by isolation oxidation regions 304. A first and a second n+ diffusion region 307, 309 are formed within the p-type bulk silicon region 303 and serve as the source and drain, respectively, of the SOI NFET 301. A gate oxide 311 and a gate metal 313 are formed over a region 315 of the p-type bulk silicon region 303 that serves as the channel of the SOI NFET 301. From FIG. 3 it can be seen that a parasitic npn transistor 317 (shown in phantom) is formed within the SOI NFET 301 having a collector-base junction formed by the second diffusion region 309 and a base-emitter junction formed by the first diffusion region 307. The base of the parasitic npn bipolar transistor is formed from the top bulk silicon region 303a.
In non-SOI devices, the top p-type bulk silicon region 303a and the bottom p-type bulk silicon region 303b form one continuous p-type bulk silicon region 303 that typically is grounded and/or is tied to the source lead. As such, the base-emitter junction of the parasitic npn transistor 317 cannot be forward biased, and the parasitic npn transistor 317 cannot turn ON. However, in SOI devices the top p-type bulk silicon region 303a is electrically isolated from the bottom p-type bulk silicon region 303b by the buried oxide 305 so that the base of the parasitic npn transistor 317 floats. Thus, under certain biasing conditions, the base-emitter junction of the parasitic npn transistor 317 can forward bias and the parasitic npn transistor 317 can turn ON (e.g. the bipolar effect). Note that if the SOI NFET 301 is ON, the source and the drain of the parasitic npn transistor 317 are connected by a conducting channel, the base-emitter junction of the parasitic npn transistor 317 cannot sufficiently forward bias to turn ON the parasitic npn transistor 317, and the bipolar effect does not result.
With reference to FIG. 1, when the CLK polarity is low and the dynamic node 107 is charged to V.sub.DD, a leakage path typically exists through the first NFET 109 that charges the first node 111 to near V.sub.DD. Alternatively, the first node 111 may be charged to near V.sub.DD due to the previous switching history. Assuming the first NFET 109, the second NFET 113, and the third NFET 117 are SOI devices, the top p-type bulk silicon region 303a of the first NFET 109 also charges to near V.sub.DD. Thereafter, if both the CLK polarity and the B input are switched high and the A input is held low, the first node 111 (and thus the source of the first NFET 109) is pulled low (e.g., is grounded). With the drain of the first NFET 109 held at V.sub.DD (via the dynamic node 107), the source of the first NFET 109 grounded and the top p-type bulk silicon region 303a of the first NFET 109 floating near V.sub.DD, the parasitic npn transistor 317 within the first NFET 109 turns ON until the charge stored within the top p-type bulk silicon region 303a is drained away. While the parasitic npn transistor 317 of the first NFET 109 is ON, charge is drained from the dynamic node 107 to ground. If sufficient charge from the dynamic node 107 is drained to ground before the parasitic npn transistor 317 turns OFF, the voltage of the dynamic node 107 will fall below the switching threshold of the inverter 123, and the traditional stacked circuit lolls output will erroneously switch to a high logic state.
With reference to FIG. 2, the third PFET 203 guarantees that the first node 111 is charged to V.sub.DD when the CLK polarity is low. Thus, the conventional pre-charged stacked circuit 201 is more susceptible to the bipolar effect than is the traditional stacked circuit 101 when the CLK polarity and the B input are switched high while the A input is held low.
FIG. 4 is a schematic diagram of a conventional top clock stacked circuit 401 that reduces the deleterious consequences of the bipolar effect within the traditional stacked circuit 101 of FIG. 1. The conventional top clock stacked circuit 401 is identical to the traditional stacked circuit 101 with the exception that the third NFET 117 has been moved from the bottom to the top of the stack 103 as shown.
In operation, when the CLK polarity is low and the dynamic node 107 is charged to V.sub.DD, a leakage path typically exists through the third NFET 117 that charges the first node 111 and the top p-type bulk silicon region 303a of the third NFET 117 to near V.sub.DD. Thereafter, if both the A input and the B input are switched high while the CLK polarity is low, the first node 111 (and thus the source of the third NFET 117) is pulled low. With the drain of the third NFET 117 held at V.sub.DD via the dynamic node 107, the source of the third NFET 117 grounded and the top p-type bulk silicon region 303a of the third NFET 117 floating near V.sub.DD, the parasitic npn transistor 317 within the third NFET 117 turns ON. However, because the CLK polarity is low, the first PFET 119 of the dynamic node pre-charge circuit 105 is ON and the dynamic node 107 thereby is maintained at V.sub.DD as the charge within the top p-type bulk silicon region 303a is drained away. Therefore, the bipolar effect within the third NFET 117 has no effect on the output of the conventional top clock stacked circuit 401.
Another bipolar effect nonetheless can occur within the conventional top clock stacked circuit 401 that affects the output of the conventional top clock stacked circuit 401. If the CLK polarity is low, the first node 111 and the second node 115 may charge to a positive voltage (e.g., via leakage paths through the first and the third NFETS 109, 117). Thereafter, if the CLK polarity is switched high, the A input is held low, and the B input is switched high, the drain of the first NFET 109 is coupled to V.sub.DD via the dynamic node 107, the source of the first NFET 109 is grounded and the top p-type bulk silicon region 303a of the first NFET 109 floats at a positive voltage. Thus, the parasitic npn transistor 317 within the first NFET 109 may turn ON and sufficient charge may be drained from the dynamic node 107 by the parasitic npn transistor 317 to pull the dynamic node 107 below the switching threshold of the inverter 123 so that the conventional top clock stacked circuit 401's output is erroneously switched to a high logic state.
The conventional top clock stacked circuit 401 also suffers from charge sharing. If the first node 111 and the second node 115 are at a low voltage and the dynamic node 107 is charged to V.sub.DD, and if the CLK polarity is switched high while the A and the B inputs are held low, charge will be transferred from the dynamic node 107 to the first node 111. If sufficient charge is transferred from the dynamic node 107 to pull the voltage of the dynamic node 107 below the switching threshold of the inverter 123, an erroneous high logic state will be output by the conventional top clock stacked circuit 401.
Accordingly, a need exists for a method and apparatus for preventing both charge sharing and any deleterious bipolar effect in stacked SOI circuits. Such a method and apparatus will greatly improve the reliability of stacked SOI circuits.